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lint, которая вызывает Verilator с параметром --lint-only. Это полезно для быстрого анализа исходных файлов Verilog/SystemVerilog и проверки на наличие проблем. Это можно использовать для проверки ваших источников, даже если вы не используете Verilator для моделирования.","type":"unstyled","key":"6pmle"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[],"text":"Наконец, есть цель make clean, которая удаляет весь мусор, созданный в процессе сборки.","type":"unstyled","key":"255iu"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[],"text":"И со всем этим давайте заставим этот испытательный стенд сиять.","type":"unstyled","key":"v461"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":36,"offset":0,"style":"BOLD"}],"text":"Рандомизированные начальные значения","type":"unstyled","key":"bpuo5"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[],"text":"Одним из наблюдений из части 1 было то, что Verilator является симулятором двух состояний, а это означает, что он поддерживает только логические значения 1 и 0 и не поддерживает X (и только ограниченную поддержку Z). Поэтому Verilator по умолчанию инициализирует все сигналы равными 0, что можно увидеть на рис. 1 из наших предыдущих результатов моделирования:","type":"unstyled","key":"8lquf"},{"data":{"image":{"id":"652ce5f1b24ca50a26b4159c"}},"depth":0,"entityRanges":[],"inlineStyleRanges":[],"text":"Рис. 1: По умолчанию все инициализировано до 0","type":"atomic:image","key":"eglhf"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":45,"offset":584,"style":"ITALIC"}],"text":"Кроме того, если у вас есть код, который присваивает X проводу или регистру, то по умолчанию он также получает значение 0.Однако мы можем изменить это поведение с помощью параметров командной строки — мы можем заставить Verilator инициализировать все сигналы равными 1 или, что еще лучше, случайным значением. Это позволит нам проверить, работает ли наш сигнал сброса, как только мы добавим его в тестовую среду.Чтобы наш тестовый стенд инициализировал сигналы случайными значениями, нам сначала нужно вызвать Verilated::commandArgs(argc, argv); перед созданием объекта DUT:\n\nint main(int argc, char** argv, char** env) {","type":"unstyled","key":"5g19q"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":35,"offset":0,"style":"ITALIC"}],"text":"Verilated::commandArgs(argc, argv);","type":"unstyled","key":"fgrmv"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":21,"offset":0,"style":"ITALIC"}],"text":"Valu *dut = new Valu;","type":"unstyled","key":"1ns1q"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":5,"offset":0,"style":"ITALIC"},{"length":100,"offset":173,"style":"ITALIC"}],"text":"<...>\n\nЗатем нам нужно обновить нашу команду сборки цели проверки, добавив --x-assign unique и --x-initial unique. Строка 31 нашего Makefile теперь должна выглядеть так:\n\nverilator -Wall --trace --x-assign unique --x-initial unique -cc $(MODULE).sv --exe tb_$(MODULE).cpp","type":"unstyled","key":"f7ijg"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":45,"offset":227,"style":"ITALIC"}],"text":"Наконец, нам нужно передать +verilator+rand+reset+2 нашему исполняемому файлу моделирования, чтобы установить случайный метод инициализации сигнала во время выполнения. Это означает изменение строки 21 в нашем Makefile на:\n\n@./obj_dir/V$(MODULE) +verilator+rand+reset+2","type":"unstyled","key":"cnl6g"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[],"text":"Теперь, если мы сделаем чистые и создадим волны, мы увидим, что теперь сигналы инициализируются случайными значениями в начале симуляции:","type":"unstyled","key":"9mjs"},{"data":{"image":{"id":"652ce606127cf366bd728049"}},"depth":0,"entityRanges":[],"inlineStyleRanges":[],"text":"Рис. 2: Случайная инициализая","type":"atomic:image","key":"2j4v1"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":30,"offset":95,"style":"BOLD"},{"length":34,"offset":284,"style":"ITALIC"}],"text":"Теперь, когда сигналы рандомизированы, мы можем взглянуть на применение нашего сигнала сброса.\n\nСброс тестируемого устройства\nЧтобы сбросить наше тестируемое устройство и его входные сигналы, мы обновляем основной цикл нашего тестового стенда, чтобы он выглядел следующим образом:\n\nwhile (sim_time < MAX_SIM_TIME) {","type":"unstyled","key":"350bv"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":13,"offset":0,"style":"ITALIC"}],"text":"dut->rst = 0;","type":"unstyled","key":"fviso"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":33,"offset":0,"style":"ITALIC"}],"text":"if(sim_time > 1 && sim_time < 5){","type":"unstyled","key":"e4idn"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":13,"offset":0,"style":"ITALIC"}],"text":"dut->rst = 1;","type":"unstyled","key":"6l9ot"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":14,"offset":0,"style":"ITALIC"}],"text":"dut->a_in = 0;","type":"unstyled","key":"5pm90"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":14,"offset":0,"style":"ITALIC"}],"text":"dut->b_in = 0;","type":"unstyled","key":"ag4es"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":15,"offset":0,"style":"ITALIC"}],"text":"dut->op_in = 0;","type":"unstyled","key":"mnt7"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":18,"offset":0,"style":"ITALIC"}],"text":"dut->in_valid = 0;","type":"unstyled","key":"27hvm"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":1,"offset":0,"style":"ITALIC"}],"text":"}","type":"unstyled","key":"8no0m"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":14,"offset":0,"style":"ITALIC"}],"text":"dut->clk ^= 1;","type":"unstyled","key":"7078p"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":12,"offset":0,"style":"ITALIC"}],"text":"dut->eval();","type":"unstyled","key":"8qqnc"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":24,"offset":0,"style":"ITALIC"}],"text":"m_trace->dump(sim_time);","type":"unstyled","key":"fudb2"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":11,"offset":0,"style":"ITALIC"}],"text":"sim_time++;","type":"unstyled","key":"6dvli"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":1,"offset":0,"style":"ITALIC"}],"text":"}\n\nВ строке 3 я произвольно выбрал, что хочу, чтобы мой сброс происходил между тактовыми фронтами 3 и 5. Вы, конечно, можете настроить это, если требуется.В строке 4 устанавливается высокий уровень сброса, а в последующих линиях все входы ИУ сбрасываются на 0.Строки 11-14 не изменяются. Мы ставим галочку на часах и увеличиваем счетчик времени.Строка 2 добавляется для сброса счетчика обратно в 0 при последующих итерациях цикла. Вместе строки 2-3-4 будут эквивалентны следующему коду SystemVerilog:always_comb begin","type":"unstyled","key":"7lva1"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[],"text":"dut.rst = 1'b0;","type":"unstyled","key":"f6272"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[],"text":"if (sim_time >= 3 && sim_time < 6) begin","type":"unstyled","key":"cvvs3"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[],"text":"dut.rst = 1'b1;","type":"unstyled","key":"eeaki"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[],"text":"end","type":"unstyled","key":"22l33"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[],"text":"end","type":"unstyled","key":"cdp5l"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[],"text":"Повторный запуск симуляции теперь дает нам это:","type":"unstyled","key":"1kbe0"},{"data":{"image":{"id":"652ce61c816f970013c4a2b2"}},"depth":0,"entityRanges":[],"inlineStyleRanges":[],"text":"Рис.3 Сигнал сброса в дейтсвии","type":"atomic:image","key":"dj89m"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":49,"offset":194,"style":"ITALIC"}],"text":"Как видно из рисунка 3, наш сигнал сброса успешно сгенерирован в тестовом стенде. Чтобы сделать основной цикл немного чище, давайте переместим элементы сброса в отдельную функцию вне main():\n\nvoid dut_reset (Valu *dut, vluint64_t &sim_time){","type":"unstyled","key":"ajgn1"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":13,"offset":0,"style":"ITALIC"}],"text":"dut->rst = 0;","type":"unstyled","key":"8d8rn"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":34,"offset":0,"style":"ITALIC"}],"text":"if(sim_time >= 3 && sim_time < 6){","type":"unstyled","key":"7tck6"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":13,"offset":0,"style":"ITALIC"}],"text":"dut->rst = 1;","type":"unstyled","key":"9d13r"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":14,"offset":0,"style":"ITALIC"}],"text":"dut->a_in = 0;","type":"unstyled","key":"e2s5d"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":14,"offset":0,"style":"ITALIC"}],"text":"dut->b_in = 0;","type":"unstyled","key":"epf0t"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":15,"offset":0,"style":"ITALIC"}],"text":"dut->op_in = 0;","type":"unstyled","key":"8pkvi"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":18,"offset":0,"style":"ITALIC"}],"text":"dut->in_valid = 0;","type":"unstyled","key":"b7bqj"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":1,"offset":0,"style":"ITALIC"}],"text":"}","type":"unstyled","key":"b046s"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":1,"offset":0,"style":"ITALIC"}],"text":"}","type":"unstyled","key":"aqseo"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":33,"offset":50,"style":"ITALIC"}],"text":"Затем добавляем вызов dut_reset в основной цикл:\n\nwhile (sim_time < MAX_SIM_TIME) {","type":"unstyled","key":"cnvd5"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":25,"offset":0,"style":"ITALIC"}],"text":"dut_reset(dut, sim_time);","type":"unstyled","key":"3tplj"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":14,"offset":0,"style":"ITALIC"}],"text":"dut->clk ^= 1;","type":"unstyled","key":"15cb6"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":12,"offset":0,"style":"ITALIC"}],"text":"dut->eval();","type":"unstyled","key":"eo25n"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":24,"offset":0,"style":"ITALIC"}],"text":"m_trace->dump(sim_time);","type":"unstyled","key":"fts4f"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":11,"offset":0,"style":"ITALIC"}],"text":"sim_time++;","type":"unstyled","key":"2i666"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":1,"offset":0,"style":"ITALIC"}],"text":"}","type":"unstyled","key":"460ao"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":16,"offset":101,"style":"BOLD"},{"length":33,"offset":195,"style":"ITALIC"}],"text":"Теперь, когда наш сброс сработал, давайте взглянем на некоторые реальные стимулы и проверочный код.\n\nБазовая проверка\nНа данный момент у нас есть следующее в нашем основном цикле моделирования:\n\nwhile (sim_time < MAX_SIM_TIME) {","type":"unstyled","key":"o4os"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":25,"offset":0,"style":"ITALIC"}],"text":"dut_reset(dut, sim_time);","type":"unstyled","key":"3k0g5"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":14,"offset":0,"style":"ITALIC"}],"text":"dut->clk ^= 1;","type":"unstyled","key":"6jp6a"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":12,"offset":0,"style":"ITALIC"}],"text":"dut->eval();","type":"unstyled","key":"et7br"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":24,"offset":0,"style":"ITALIC"}],"text":"m_trace->dump(sim_time);","type":"unstyled","key":"cvlrm"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":11,"offset":0,"style":"ITALIC"}],"text":"sim_time++;","type":"unstyled","key":"b71cq"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":1,"offset":0,"style":"ITALIC"}],"text":"}","type":"unstyled","key":"8jfr"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":15,"offset":602,"style":"BOLD"},{"length":24,"offset":875,"style":"ITALIC"},{"length":27,"offset":900,"style":"ITALIC"}],"text":"Теперь, если бы мы моделировали тестовый стенд Verilog/SystemVerilog в качестве dut вместо нашего модуля alu, мы могли бы добавить проверку для Verilated::gotFinish() и остановить симуляцию, если для нее установлено значение true. Это происходит, когда $finish() вызывается из Verilog/SystemVerilog. Тогда нашего тестового стенда C++ будет достаточно для имитации тестового стенда Verilog/SystemVerilog.Однако этого нам будет недостаточно, так как нам нужно вставить стимул и проверочный код где-то в основной цикл тестового стенда C++, чтобы запустить и проверить наше тестируемое устройство.\n\nСчётчик тактов\nЕсть много способов снять шкуру с мертвой лошади одним камнем, но вот что мы собираемся сделать сейчас:Во-первых, мы создадим новую переменную для подсчета положительных фронтов тактового сигнала. Эта переменная будет того же типа, что и sim_time: \n\nvluint64_t sim_time = 0;\nvluint64_t posedge_cnt = 0;","type":"unstyled","key":"1gitq"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":41,"offset":84,"style":"ITALIC"}],"text":"Затем мы модифицируем наш код генерации ребер, добавив счетчик положительных ребер:\ndut->clk ^= 1; // Invert clock","type":"unstyled","key":"5odua"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":61,"offset":0,"style":"ITALIC"}],"text":"dut->eval(); // Evaluate dut on the current edge","type":"unstyled","key":"3hv56"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":18,"offset":0,"style":"ITALIC"}],"text":"if(dut->clk == 1){","type":"unstyled","key":"566gh"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":62,"offset":0,"style":"ITALIC"}],"text":"posedge_cnt++; // Increment posedge counter if clk is 1","type":"unstyled","key":"2eu2g"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":1,"offset":0,"style":"ITALIC"}],"text":"}","type":"unstyled","key":"7i5es"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":49,"offset":0,"style":"ITALIC"}],"text":"m_trace->dump(sim_time); // Dump to waveform.vcd","type":"unstyled","key":"4civ7"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":52,"offset":0,"style":"ITALIC"}],"text":"sim_time++; // Advance simulation time\n\nДобавление этого счетчика между eval и dump дает нам что-то похожее на следующее в Verilog:","type":"unstyled","key":"15r5i"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":26,"offset":0,"style":"ITALIC"}],"text":"initial posedge_cnt <= '0;","type":"unstyled","key":"5fsof"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":44,"offset":0,"style":"ITALIC"}],"text":"always_ff @ (posedge clk, posedge rst) begin","type":"unstyled","key":"5rd8n"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":34,"offset":0,"style":"ITALIC"}],"text":"posedge_cnt <= posedge_cnt + 1'b1;","type":"unstyled","key":"dsil2"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":3,"offset":0,"style":"ITALIC"}],"text":"end","type":"unstyled","key":"3vhq6"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[],"text":"И на этом этапе мы, наконец, можем приступить к проверке нашего ALU.","type":"unstyled","key":"esrtn"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":42,"offset":0,"style":"BOLD"}],"text":"Примитивные тестируемые стимулы и проверки","type":"unstyled","key":"4hamd"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[],"text":"Давайте еще раз взглянем на ожидаемые формы сигналов для нашего ALU:","type":"unstyled","key":"1c443"},{"data":{"image":{"id":"652ce632815fc705004353c9"}},"depth":0,"entityRanges":[],"inlineStyleRanges":[],"text":"Рис. 4: Ожидаемое поведение ALU ","type":"atomic:image","key":"7j8ev"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":31,"offset":241,"style":"ITALIC"}],"text":"Игнорируя входы a, b и операции, а также выходные данные, давайте сначала проверим, что наш входной допустимый сигнал распространяется на выход.Мы знаем, что у нас есть 2 этапа регистрации, которые в упрощенном виде будут выглядеть так:\n\nalways_ff @ (posedge clk) begin","type":"unstyled","key":"5bqpf"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":23,"offset":0,"style":"ITALIC"}],"text":"in_valid_r <= in_valid;","type":"unstyled","key":"eibgk"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":25,"offset":0,"style":"ITALIC"}],"text":"out_valid <= out_valid_r;","type":"unstyled","key":"9ujsq"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":3,"offset":0,"style":"ITALIC"}],"text":"end","type":"unstyled","key":"7j361"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":33,"offset":222,"style":"ITALIC"}],"text":"Таким образом, если мы применили 1 к in_valid на 5-м положительном фронте тактов, мы должны увидеть 1 на out_valid после двух тактов, или, другими словами, на 7-м положительном фронте тактов. Вот как мы это проверяем:\n\nwhile (sim_time < MAX_SIM_TIME) {","type":"unstyled","key":"bqikg"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":25,"offset":0,"style":"ITALIC"}],"text":"dut_reset(dut, sim_time);","type":"unstyled","key":"60ivj"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":14,"offset":0,"style":"ITALIC"}],"text":"dut->clk ^= 1;","type":"unstyled","key":"dlg91"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":12,"offset":0,"style":"ITALIC"}],"text":"dut->eval();","type":"unstyled","key":"3ba9u"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":18,"offset":0,"style":"ITALIC"}],"text":"dut->in_valid = 0;","type":"unstyled","key":"3pusi"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":19,"offset":0,"style":"ITALIC"}],"text":"if (dut->clk == 1){","type":"unstyled","key":"7fmss"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":14,"offset":0,"style":"ITALIC"}],"text":"posedge_cnt++;","type":"unstyled","key":"dcgi"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":22,"offset":0,"style":"ITALIC"}],"text":"if (posedge_cnt == 5){","type":"unstyled","key":"dqp1r"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":53,"offset":0,"style":"ITALIC"}],"text":"dut->in_valid = 1; // assert in_valid on 5th cc","type":"unstyled","key":"8fvuv"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":1,"offset":0,"style":"ITALIC"}],"text":"}","type":"unstyled","key":"cah4p"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":22,"offset":0,"style":"ITALIC"}],"text":"if (posedge_cnt == 7){","type":"unstyled","key":"rbc3"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":52,"offset":0,"style":"ITALIC"}],"text":"if (dut->out_valid != 1) // check in_valid on 7th cc","type":"unstyled","key":"5jkpo"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":35,"offset":0,"style":"ITALIC"}],"text":"std::cout << \"ERROR!\" << std::endl;","type":"unstyled","key":"pbn1"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":1,"offset":0,"style":"ITALIC"}],"text":"}","type":"unstyled","key":"8c4c8"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":1,"offset":0,"style":"ITALIC"}],"text":"}","type":"unstyled","key":"cs87e"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":24,"offset":0,"style":"ITALIC"}],"text":"m_trace->dump(sim_time);","type":"unstyled","key":"ebfln"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":11,"offset":0,"style":"ITALIC"}],"text":"sim_time++;","type":"unstyled","key":"6j36f"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":1,"offset":0,"style":"ITALIC"},{"length":17,"offset":59,"style":"ITALIC"}],"text":"}\n\nТо, что выполняет выделенный код, будет похоже на это:\n\nalways_comb begin","type":"unstyled","key":"1ol7k"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":13,"offset":0,"style":"ITALIC"}],"text":"in_valid = 0;","type":"unstyled","key":"fm921"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":21,"offset":0,"style":"ITALIC"}],"text":"if (posedge_cnt == 5)","type":"unstyled","key":"ahqoj"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":13,"offset":0,"style":"ITALIC"}],"text":"in_valid = 1;","type":"unstyled","key":"af7m7"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":21,"offset":0,"style":"ITALIC"}],"text":"if (posedge_cnt == 7)","type":"unstyled","key":"e3b0b"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":45,"offset":0,"style":"ITALIC"}],"text":"assert (out_valid == 1) else $error(\"ERROR!\")","type":"unstyled","key":"6vkjt"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":3,"offset":0,"style":"ITALIC"}],"text":"end\n\nГлавное здесь — убедиться, что код стимулов/проверки, который вы пишете, следует следующему порядку операций:\n\n1.Перейдите на 1 такт, оцените, чтобы создать положительный фронт, а затем установите входы/проверьте выходы перед сбросом и увеличением времени моделирования.","type":"unstyled","key":"fr0hh"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[],"text":"2.При следующем положительном фронте тактового сигнала внутри цикла while() входные данные, установленные ранее, будут распространяться на дизайн во время eval, а затем сразу после eval входные данные должны быть сброшены к их значениям по умолчанию.","type":"unstyled","key":"cdqbe"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":26,"offset":702,"style":"ITALIC"}],"text":"Мониторинг сигналов, подобный утверждениюУстановка in_valid на 5-м фронте и проверка того, что out_valid равно 1, безусловно, работает, но если мы хотим проверять валидность на большем количестве тактов, нам нужно добавить гораздо больше проверок. Кроме того, мы не проверяем, что значение out_valid равно 0 там, где оно должно быть, а это означает, что значение out_valid может застрять на значении 1, и тестовый стенд не выйдет из строя. Таким образом, наш проверочный код можно было бы значительно улучшить, написав код на C++ для непрерывного мониторинга in_valid и out_valid, аналогично тому, как работают утверждения SystemVerilog.Мы можем написать функцию для этого следующим образом:\n\n#define VERIF_START_TIME 7","type":"unstyled","key":"9hl2s"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":54,"offset":0,"style":"ITALIC"}],"text":"void check_out_valid(Valu *dut, vluint64_t &sim_time){","type":"unstyled","key":"42tah"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":64,"offset":0,"style":"ITALIC"}],"text":"static unsigned char in_valid = 0; //in valid from current cycle","type":"unstyled","key":"11qf7"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":55,"offset":0,"style":"ITALIC"}],"text":"static unsigned char in_valid_d = 0; //delayed in_valid","type":"unstyled","key":"2umn7"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":66,"offset":0,"style":"ITALIC"}],"text":"static unsigned char out_valid_exp = 0; //expected out_valid value","type":"unstyled","key":"9mo30"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":35,"offset":0,"style":"ITALIC"}],"text":"if (sim_time >= VERIF_START_TIME) {","type":"unstyled","key":"c7aag"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":18,"offset":0,"style":"ITALIC"}],"text":"// note the order!","type":"unstyled","key":"asp17"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":27,"offset":0,"style":"ITALIC"}],"text":"out_valid_exp = in_valid_d;","type":"unstyled","key":"ea9i7"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":22,"offset":0,"style":"ITALIC"}],"text":"in_valid_d = in_valid;","type":"unstyled","key":"chh9n"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":25,"offset":0,"style":"ITALIC"}],"text":"in_valid = dut->in_valid;","type":"unstyled","key":"ahopv"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":38,"offset":0,"style":"ITALIC"}],"text":"if (out_valid_exp != dut->out_valid) {","type":"unstyled","key":"15rvs"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":42,"offset":0,"style":"ITALIC"}],"text":"std::cout << \"ERROR: out_valid mismatch, \"","type":"unstyled","key":"9ij7b"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":34,"offset":0,"style":"ITALIC"}],"text":"<< \"exp: \" << (int)(out_valid_exp)","type":"unstyled","key":"720i3"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":37,"offset":0,"style":"ITALIC"}],"text":"<< \" recv: \" << (int)(dut->out_valid)","type":"unstyled","key":"b7mrl"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":41,"offset":0,"style":"ITALIC"}],"text":"<< \" simtime: \" << sim_time << std::endl;","type":"unstyled","key":"ffsds"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":1,"offset":0,"style":"ITALIC"}],"text":"}","type":"unstyled","key":"1a2ke"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":1,"offset":0,"style":"ITALIC"}],"text":"}","type":"unstyled","key":"2cgp1"},{"data":{},"depth":0,"entityRanges":[],"inlineStyleRanges":[{"length":33,"offset":541,"style":"ITALIC"}],"text":"}\n\nVERIF_START_TIME необходимо, чтобы убедиться, что мы не запускаем этот код проверки до или во время сброса, чтобы предотвратить обнаружение ложных ошибок. Если вы обратитесь к рис. 5, вы увидите, что rst возвращается к 0 через 6 пс (равно sim_time, равному 6), поэтому sim_time, равное 7, — это то место, где мы должны начать проверку нашей достоверности.Код проверки довольно прост — он просто моделирует конвейер регистрации между in_valid и out_valid. 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